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Cypress Semiconductor /psoc63 /SCB0 /UART_TX_CTRL

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Interpret as UART_TX_CTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0STOP_BITS 0 (PARITY)PARITY 0 (PARITY_ENABLED)PARITY_ENABLED 0 (RETRY_ON_NACK)RETRY_ON_NACK

Description

UART transmitter control

Fields

STOP_BITS

Stop bits. STOP_BITS + 1 is the duration of the stop period in terms of halve bit periods. Valid range is [1, 7]; i.e. a stop period should last at least one bit period.
PARITY

Parity bit. When ‘0’, the transmitter generates an even parity. When ‘1’, the transmitter generates an odd parity. Only applicable in standard UART and SmartCard submodes.
PARITY_ENABLED

Parity generation enabled (‘1’) or not (‘0’). Only applicable in standard UART submodes. In SmartCard submode, parity generation is always enabled through hardware. In IrDA submode, parity generation is always disabled through hardware
RETRY_ON_NACK

When ‘1’, a data frame is retransmitted when a negative acknowledgement is received. Only applicable to the SmartCard submode.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data